The present invention relates to solid-state imaging apparatus for use for example in a video camera, digital still camera, etc., and more particularly relates to the solid-state imaging apparatus using an amplified solid-state imaging device having an amplification function within its imaging region.
In recent years, MOS image sensors having active element within pixel capable of forming peripheral circuits into an on-chip system are used as imaging device in the imaging apparatus for example of digital still camera. FIG. 1 shows a circuit construction of an ordinary MOS image sensor. While a plurality of pixels are two-dimensionally arranged in CMOS image sensors, only 3 pixels P11, P12, P13 arranged into 1 row by 3 columns are shown here for ease of explanation. Each pixel P11, P12, P13 respectively includes: a photodiode PD; a floating diffusion section FD11, FD12, FD13 having electrostatic capacitance; a transfer transistor M1; a reset transistor M2; an amplification transistor M311, M312, M313; and a select transistor M4. The pixels P11, P12, P13 are connected to a correlated double sampling circuit (CDS circuit) 10 respectively through a vertical signal line 31, 32, 33. The vertical signal lines 31, 32, 33 are connected respectively to one end of biasing transistors M51, M52, M53 serving as constant current supply having the other end grounded, where each biasing transistor M51, M52, M53 is controlled by a bias current regulating voltage Vbias.
The CDS circuit 10 includes: a clamp transistor M11; a sample-and-hold transistor M12; a clamp capacitor C11; and a sample-and-hold capacitor C12. The CDS circuit 10 is connected to a horizontal signal line 7 through a select transistor M6 so as to output image signal through an output amplifier 5. A transfer pulse φTR1, reset pulse φRST1, row select pulse φROW1 associated with control of the transfer transistor M1, reset transistor M2 and select transistor M4 within pixel, and a column select pulse φH1, φH2, φH3 associated with control of the column select transistor M6 are outputted respectively from a vertical scanning section 2 and a horizontal scanning section 4 under control of a timing control section 6. Further, a clamp pulse φCL and a sample-and-hold pulse φSH associated with control of the clamp transistor M11 and the sample-and-hold transistor M12 are outputted from the timing control section 6.
In thus constructed MOS image sensor, image quality degradation is caused by a variance in the threshold of the amplification transistor M311 to M313 and a reset noise of the reset transistor M2 of each pixel. At the CDS circuit 10, however, these noises are removed by taking a difference between a pixel output after reset and a pixel output after transfer of signal electric charges of the photodiode PD so that only the signal of light serving as image signal can be outputted.
With the MOS image sensor having CDS circuit, it is known that, when a high-luminance light is incident, a completely blackened image as if without any incidence of light is generated. This phenomenon will be referred to hereinafter as “black sun phenomenon”. The black sun phenomenon in MOS image sensor will now be described. FIG. 2 is a timing chart for explaining operation where the black sun phenomenon occurs when a high-luminance object is photographed. A description will be given below on an assumption that a high-luminance light is incident on the pixel P12 at a center shown in FIG. 1 and that light is scarcely incident on the pixels P11, P13 of the rest.
(1): At first in a reset period T1, the reset pulse φRST1 is driven to H level in the condition where the row select pulse φROW1 is at H level so as to fix the floating diffusion section FD11, FD12, FD13 of each pixel to a power supply voltage VDD. The clamp pulse φCL and the sample-and-hold pulse φSH of the CDS circuit 10 are also driven to H level.
(2): In a subsequent reset-sample period T2, the reset pulse φRST1 is brought to L level. At this time, while voltages VFD11, VFD13 (VFD13: not shown) of the floating diffusion section FD11, FD13 at the pixel P11, P13 where the high-luminance light is not incident do not change, the voltage VFD12 of the floating diffusion section FD12 at the pixel P12 where the high-luminance light is incident falls as shown for example due to a leaking-in of electric charges from the photodiode PD. An electric potential V32(Rst) of the vertical signal line 32 to which the pixel P12 is connected is thereby also lowered to attain (VFD12−VGS-M312). It should be noted that VGS-M312 in this case is a gate-source voltage of the amplification transistor M312 of the pixel P12. In an end period of the reset-sample period T2, then, the clamp pulse φCL of the CDS circuit 10 is brought to L level to clamp electric potential of each vertical signal line 31 to 33.
(3): In a subsequent signal transfer period T3, the transfer pulse φTR1 is driven to H level to transfer the signal electric charges of photodiode PD of each pixel P11 to P13 respectively to the floating diffusion section FD11 to FD13. At this time, since the voltage VFD12 of the floating diffusion section FD12 at the high-luminance light incident pixel P12 has already been lowered in the reset-sample period T2, it falls by only a small amount from the voltage in the reset-sample period T2 (or does not change when the voltage VFD12 of the floating diffusion section FD12 has been lowered to a lowest level possible due to the leaking-in of electric charges) even when the electric charges of the photodiode PD is transferred. Therefore, the electric potential V32(Sig) of the vertical signal 32 also changes only by a small amount. It should be noted that a change scarcely occurs at this time also in the electric potentials of the other vertical signal lines 31, 33, since it is supposed that light is scarcely incident on the pixels P11, P13.
(4): In a subsequent signal sampling period T4, a difference potential [V32(Rst)−V32(Sig)] is retained at the sample-and-hold capacitor C12 by a processing operation of the CDS circuit 10. Next, the difference potential processed at the CDS circuit 10 is outputted as image signal through the column select transistor M6 and the output amplifier M5. At this time, in the pixel P12 where the high-luminance light is incident, the difference potential [V32(Rst)−V32(Sig)] by the CDS processing is small due to change in the electric potential V32(Rst) of the vertical signal line 32 in the reset-sample period T2, whereby a darkened output is outputted as image signal and the black sun phenomenon occurs.
The problem of occurrence of the black sun phenomenon can be eliminated with respect to still picture taking by providing a mechanical shutter. At the time of taking image without using a mechanical shutter for example in taking a moving picture, however, its occurrence cannot be avoided.
Further, when a high-luminance light is incident, its effect may in some cases occur also in a pixel region outside the pixel into which an intense light has entered. FIG. 3 is a timing chart for explaining an operation in the occurrence of a highlight transverse stripe phenomenon that occurs on the periphery of a pixel on which the high-luminance light is incident. In this case, too, a description will be given below on an assumption that a high-luminance light is incident on the pixel P12 at a center shown in FIG. 1 and that light is scarcely incident on the pixels P11, P13 of the rest. It is also supposed in this case that the black sun phenomenon does not occur.
(1): At first in a reset period T1, the reset pulse φRST1 is similarly driven to H level in the condition where the row select pulse φROW1 is at H level so as to fix the voltages VFD11 to VFD13 of the floating diffusion section FD11, FD12, FD13 of each pixel to a power supply voltage VDD. The clamp pulse φCL and the sample-and-hold pulse φSH of the CDS circuit 10 are also driven to H level.
(2): In a subsequent reset-sample period T2, the clamp pulse φCL of the CDS circuit 10 is brought to L level toward an end of the period to clamp the voltage of the floating diffusion section FD11 to FD13 of each pixel to the CDS circuit 10 through the vertical signal line 31 to 33.
(3): In a subsequent signal transfer period T3, the transfer pulse φTR1 is driven to H level to transfer the signal electric charges of photodiode PD of each pixel P11 to P13 respectively to the floating diffusion section FD11 to FD13. Since the amount of signal electric charges then is large at the high-luminance light incident pixel P12, the electric potential VFD12 of its floating diffusion section FD12 is greatly lowered from the power supply voltage VDD. The electric potential V32 of the vertical signal line 32 to which the pixel P12 is connected, therefore, attains (VFD−VGS-M312), i.e. greatly lowered. Since a drain-source voltage of the biasing transistor M52 connected to the vertical signal line 32 is thereby made smaller, an electric current flowing through the biasing transistor M52 is reduced. A voltage drop due to GND resistance of a ground line connected in common to the sources of the biasing transistors M51 to M53 is thereby reduced so that the gate-source voltages of the biasing transistors M51, M53 connected to the vertical signal lines 31, 33 are increased so as to increase the electric currents flowing through the vertical signal lines 31, 33. The gate-source voltages of the amplification transistors M311, M313 of the pixels P11, P13 are thereby increased so that the electric potentials V31, V33 of the vertical signal lines 31, 33 are lowered by ΔV in relation to a reset level output (VDD).
(4): In a subsequent signal sampling period T4, the difference between a reset potential and a potential of reading light signal after transfer on the vertical signal lines 31 to 33 is outputted as image signal through the column select transistor M6 and the output amplifier 5 by means of a processing operation of the CDS circuit 10. At this time, a difference in potential ΔV from the reset level is detected at the pixels P11, P13 located on the periphery of the high-luminance light incident pixel P12 due to change in electric current through the ground line connected to the biasing transistor M52 as described; this then results in a white float-like image and the highlight transverse stripe phenomenon occurs in the image signals.
In this manner, when an image of a window chart is taken with a MOS image sensor, images as shown in FIGS. 4B to 4D are to be obtained due to the black sun phenomenon and the highlight transverse stripe phenomenon. FIG. 4A shows an object pattern having a high-luminance light at its center; FIG. 4B shows the manner of an occurrence of the black sun phenomenon due to change in reset potential; FIG. 4C shows the manner of an occurrence of the highlight transverse stripe phenomenon due to signal potential change; and FIG. 4D shows the manner of an occurrence of the black sun phenomenon and the highlight transverse stripe phenomenon in combination.
A method as shown in the following has been proposed in Japanese Patent Application Laid-Open 2007-20156 as method for preventing an occurrence of the black sun phenomenon and the highlight transverse stripe phenomenon in the above described MOS image sensor. Particularly in the proposed method, as shown in FIG. 5, clip circuits 71 to 73 capable of limiting the electric potential of the vertical signal line selectively to a first and to a second electric potential are provided respectively on each vertical signal line 31 to 33, whereby control is correspondingly effected so as not to bring a pixel output after reset of pixel to a level lower than the first potential and not to bring a pixel output after transfer of signal electric charges to a level lower than the second potential. It should be noted that the clip circuits 71 to 73 respectively include a clip transistor M71 to M73 and a clip select transistor M81 to M83. The gate of the clip transistor M71 to M73 is then connected to a clip voltage Vclip and the drain to a power supply voltage VDD; a clip select pulse φROWD is applied on the gate of the clip select transistor M81 to M83 and the source thereof is connected to the vertical signal line 31 to 33. The clip voltage Vclip and the clip select pulse φROWD are to be outputted from a timing control circuit 6.
An operation of the MOS image sensor provided with thus constructed clip circuits will now be described by way of a timing chart shown in FIG. 6. In this case, too, it is supposed that a high-luminance light is incident on the pixel P12 and that light is scarcely incident on the pixels P11, P13 of its periphery.
(1): At first in a reset period T1, the select pulse φROW1 is driven to H level to previously set the clip voltage Vclip to a first level VclipH which is lower than the power supply voltage VDD but with which the black sun phenomenon does not occur. The reset pulse φRST1 is then driven to H Level to fix the floating diffusion section FD11, FD12, FD13 of each pixel to the power supply voltage VDD. Further, the clamp pulse φCL and the sample-and-hold pulse φSH of the CDS circuit 10 are also driven to H level.
(2): In a subsequent reset-sample period T2, the voltage VFD12 of the floating diffusion section FD12 is greatly lowered at the high-luminance light incident pixel P12 for example due to a leaking-in of electric charges from the photodiode FD. While the electric potential V32 of the vertical signal line 32 is also lowered to (VFD12−VGS-M312) if the clip circuits are not provided, the electric potential V32(Rst) of the vertical signal line 32 is clipped at (VclipH−VGS-M72) by the clip circuit 72 and does not fall to a lower potential than that. An occurrence of the black sun phenomenon, therefore, is avoided even with a subsequent differential processing at the CDS circuit 10. It should be noted that VGS-M72 in this case is a gate-source voltage of the clip transistor M72. Toward an end period of the reset-sample period T2, then, the clamp pulse φCL is brought to L level at the CDS circuit 10 to clamp the electric potentials of each vertical signal line 31 to 33.
(3): In a subsequent signal transfer period T3, the clip voltage Vclip is switched to a second level VclipL at which the highlight transverse stripe phenomenon does not occur, and at the same time the transfer pulse φTR1 is driven to H level. The electric charges of photodiode PD of each pixel P11 to P13 are thereby transferred respectively to the floating diffusion section FD11 to FD13. At this time, since the voltage VFD12 of the floating diffusion section FD12 at the high-luminance light incident pixel P12 has already fallen in the reset-sample period T2, only a small amount of fall from the voltage in the reset-sample period is seen of its voltage Vsig even when the electric charges of the photodiode PD is transferred. While the electric potential V32(sig) of the vertical signal line 32, if not clipped, is changed to (Vsig−VGS-M312), the electric potential V32(sig) of the vertical signal line 32 is clipped at (VclipL−VGS-M72) because the second level VclipL is set at the clip circuit. A fall by ΔV from the reset level output (VDD) in the electric potentials V31, V33 of the vertical signal lines 31, 33 is thereby avoided so that an occurrence of the highlight transverse stripe is avoided.
(4): In a subsequent signal sampling period T4, a difference between the reset potential of the vertical signal line 31 to 33 and the potential of reading light signal after transfer is retained at the sample-and-hold capacitor C12 by a processing operation of the CDS circuit 10, and is then outputted through the column select transistor M6 and the output amplifier 5 as an image signal where the black sun phenomenon and the highlight transverse stripe phenomenon are prevented.
By providing clip circuit as the above, when the electric potential V32(Rst) [=(VFD12−VGS-M312)] at the time of reset of the vertical signal line 32 has become smaller than the output voltage (VclipH−VGS-M72) of clip circuit, and when the electric potential V32(sig) [=(VFD12−VGS-M312)] at the time of reading signal has become smaller than the output voltage (VclipL−VGS-M72) of clip circuit, the electric potentials of the vertical signal lines are clipped by the output voltage of the respective clip circuits so that an occurrence of the black sun phenomenon and the highlight transverse stripe phenomenon can be avoided.